1. Technical Field
The present invention relates generally to integrated circuits (ICs) and, in particular, to a method for IC fault analysis using programmable built-in self test and optical emission.
2. Background Description
The invention described herein resulted from a debug problem referred to as the xe2x80x9cHoley Shmoo problemxe2x80x9d. The problem developed during the design of the IBM System/390 G6 637 MHz microprocessor chip. The problem and the methodology used to successfully solve the problem will be described herein.
Shmoo plotting began in the early 1970""s and has since been widely used in characterizing device performance against various parameters. Shmoo plotting (in test characterizations) probably took its name based on either the appearance or the eternally obliging nature of Al Capp""s cartoon figure Shmooxe2x80x9d, as noted by Baker et al., in xe2x80x9cShmoo Plotting: The Black Art of IC Testingxe2x80x9d, IEEE Design and Test of Computers, pp. 90-97 July-September 1997.
Common to characterization is the Shmoo plotting of a device""s frequency performance or cycle time vs. voltage. The xe2x80x9cHoley Shmooxe2x80x9d debug focused on problems (holes) in this type of Shmoo plot. This problem has 2 distinct phases as the microprocessor design was migrated from an older CMOS process technology into a newer, faster one.
A description of the problem will now be given. The IBM System/390 G6 microprocessor chip is used in the S/390 G6 mainframe computer system which was released in May 1999. The speed of this processor is 555 MHz (1.8 ns cycle) for the xe2x80x9cStandardxe2x80x9d systems and 637 MHz (1.57 ns cycle) for the faster xe2x80x9cTurbo xe2x80x9d systems. The L1 Cache embedded SRAM core on this microprocessor exhibited a peculiar cycle-time limitation that came to be described as the xe2x80x9cHoley Shmoo Problemxe2x80x9d.
FIGS. 1A and 1B are programmable built-in self test (RAMBIST) Shmoo plots for the same integrated circuit, which illustrate the xe2x80x9cHoley Shmooxe2x80x9d behavior of the L1 Cache embedded static random access memory (SRAM). The plots are of cycle time versus voltage. The on chip cycle time is xe2x85x9th the time shown on the x-axis (ns).
The net of the problem was that the L1 Cache embedded SRAM was not meeting its cycle time specification. Specific RAMBIST Shmoos of the phenomenon were intermittent (holey) with voltage and cycle time. The degraded cycle time was restricted only to consecutive write patterns to the L1 Cache and did not seem to affect the several other embedded SRAMs on the chip. The L1 Cache SRAM began to intermittently fail when repeated data write patterns were applied to it at faster cycle times. The failure point occurred at much slower cycle times than were anticipated resulting in much slower pass/fail Shmoo plots which contained many non-repeatable holes at the pass/fail boundary. This is how the problem gained its unique name.
The problem was first seen in the IBM CMOS6X (0.25 um) process technology and appeared to be defect based. FIGS. 2A and 2B RAMBIST Shmoo plots for a normal and a xe2x80x9cHoley Shmooxe2x80x9d IC, respectively, wherein the two ICs both have the same potential speed based on their flush delays. Flush delay is a method of measuring chip potential speed by measuring the propagation delay of a signal through a long chain of scannable latches which have their scan clocks held on, i.e. flushing. Chips with identical flush delays should perform very similarly in most speed based tests, barring any defects. Here, one chip appears to be xe2x80x9cnormalxe2x80x9d while the other exhibits the xe2x80x9cHoley Shmoo problemxe2x80x9d. The right most portion of the Shmoo plots indicate where all tests pass, the black portion is where the Logic BIST (LBIST) speed test began to fail, and the white portion is where the RAMBIST test failed due to the L1 Cache SRAM. LBIST is further described by Foote et al., in xe2x80x9cTesting the 400 MHz IBM Generation-4 CMOS Chipxe2x80x9d, Proceedings of the IEEE International Test Conference, pp. 106-114, 1997; and Foote et al., in xe2x80x9cMicroprocessor Test and Test Tool Methodology for the 500 MHZ IBM S 390 G5 Chipxe2x80x9d, Proceedings of the IEEE International Test Conference, pp. 717-726, 1998. The holes in the RAMBIST fails have been filled-in by running many RAMBIST tests targeting the problem, and overlaying their pass/fail results. The Logic BIST (LBIST) failing cycle times are nearly identical while the RAMBIST failing cycle times for the L1 Cache SRAMs differ by over 300 ps (on chip). This difference is apparently defect-based. On-chip cycle time is xe2x85x9th the x-axis time (ns).
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a method for IC fault analysis using programmable built-in self test and optical emission.
In a first aspect of the invention, there is provided a method for analyzing the functionality of an integrated circuit (IC). The method includes the step of applying a built-in self test (BIST) to the integrated circuit. The BIST includes a plurality of tests that result in the integrated circuit passing and/or failing with respect to predefined criteria. During the applying step, a substrate current of the integrated circuit is measured and analyzed as a function of at least one variable. Also during the applying step, optical emissions of the integrated circuit are measured and analyzed. Defects in the functionality of the integrated circuit are identified, based on at least one of the substrate current and the optical emissions.
In a second aspect of the invention, the at least one variable includes at least one of a clock frequency of the integrated circuit, an operating voltage of the integrated circuit, and a temperature associated with the integrated circuit.
In a third aspect of the invention, the step of measuring and analyzing the substrate current is performed for different values of the at least one variable.
In a fourth aspect of the invention, the step of applying the BIST includes the step of continuously repeating the plurality of tests.
In a fifth aspect of the invention, the step of applying the BIST includes the step of applying a continuously repeating and programmable random access memory built-in self test (RAMBIST) to the integrated circuit.
In a sixth aspect of the invention, the step of applying the RAMBIST includes the step of monitoring an occurrence of a fault in the integrated circuit, using a real time error bit in the RAMBIST.
In a seventh aspect of the invention, the step of measuring and analyzing the optical emissions includes the step of characterizing a timing fault, based upon the optical emissions being time resolved.
In an eighth aspect of the invention, the step of measuring and analyzing the optical emissions includes the step of minimizing attenuation of the optical emissions.
In a ninth aspect of the invention, wherein the optical emissions include time resolved and time integrated optical emissions and the step of measuring and analyzing the optical emissions includes the step of comparing the time resolved and time integrated optical emissions against a simulation of the integrated circuit.
In a tenth aspect of the invention, the step of measuring and analyzing the optical emissions includes the step of playing back the optical emissions as a slow motion movie.
In an eleventh aspect of the invention, the step of measuring and analyzing the optical emissions includes the step of determining the optical emissions using at least one of a photomultiplier, an infrared (IR) measuring device and a charge-coupled device (CCD).
In a twelfth aspect of the invention, the step of measuring and analyzing the optical emissions includes the step of determining the optical emissions using an infrared (IR) measuring device and at least one of a photomultiplier for time resolved detection of the optical emissions, and a charge-coupled device (CCD) for time integrated detection of the optical emissions.
In a thirteenth aspect of the invention, the step of measuring and analyzing the optical emissions includes the step of analyzing individual emission spots with respect to a design layout of the integrated circuit, each of the spots including at least one pixel.
In a fourteenth aspect of the invention, the step of measuring and analyzing the optical emissions includes the step of extracting optical waveforms.
In a fifteenth aspect of the invention, the plurality of tests are executed for different values of at least one of a clock frequency of the integrated circuit, an operating voltage of the integrated circuit, and a temperature associated with the integrated circuit.
In a sixteenth aspect of the invention, the method further includes the step of subtracting results of the plurality of tests executed at different frequencies.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.